1. Field of the Invention
The present invention relates to, of a semiconductor device fabrication process, a doping method for p-n junction formation and to a semiconductor device fabricated using the method. More particularly, the invention relates to a high-concentration doping method having an extremely shallow junction depth and to a metal-oxide-semiconductor field effect transistor (hereinafter referred to simply as MOSFET) fabricated using the method.
2. Description of the Prior Art
In the case of semiconductor large-scale-integrated circuit (LSI) devices with miniaturization of constituent elements, a high-integration level and a high-speed property have been achieved simultaneously. Also in the case of MOSFETs, improvements in the technique of reducing the size thereof have been made. With the reduction in channel length, however, the short-channel effect and a so-called hot-carrier phenomenon that is a phenomenon undesirable for the performance of transistors have been brought about conspicuously.
In order to suppress occurrence of the phenomena adversely affecting the performance of the semiconductor devices, it is required to shallow the depth of the source-drain junction. In addition, it is required to make the resistivity of the doping layers (sheet resistance) in the source and drain as low as possible in order to enhance the ability to current-drive the transistors. In view of these, in ultra-small MOSFETs, the carrier concentration of the doping layer must be high to satisfy these requirements. That is to say, ultra-small MOSFETs are required to achieve the shallow source-drain junction and low sheet resistance at the same time.
The conventional techniques of forming a shallow source-drain junction include a Combination of Low-energy Ion Implantation and Rapid Thermal Annealing Process (A. Ono et al.: 2000 symposium on VLSI Technology Digest of Technical Papers, p. 14), Plasma Doping (B. Mizuno: Oyo Butsuri (in Japanese), Vol. 70, 12, pp. 1458–1462, 2001), Elevated Source/Drain by Selective Epitaxial Growth (K. Muto: Electronic Material, Nov. Independent Vol./2002 VLSI Manufacturing and Testing Apparatus Guidebook, pp. 94–99, 2001) Solid Phase Diffusion (E. Murakami et al.: JP-A HEI 8-16765 8) and Laser Doping (K. Shibahara et al.: 2001 Solid State Devices and Materials, p. 236).
However, the junction depth and sheet resistance obtained by the conventional techniques are 20 nm at most and around 400 Ω/square, respectively. In order to achieve the fabrication of further small transistors, there is a need to develop a technique of forming a shallower source-drain junction and a doping layer having a higher carrier density over the conventional techniques.
In addition, great electric power is required to perform the conventional processes mentioned above, particularly the rapid thermal annealing process. This poses a problem from the standpoint of energy efficiency. The high temperature required in the conventional processes also makes it unable to use new materials having low heat resistance, such as high dielectric constant gate insulator materials and metal gate materials.
Furthermore, since any of the aforementioned conventional techniques introduces impurity atoms into a semiconductor through a stochastic process, such as ion implantation or thermal diffusion, it is unavoidable as an inevitable consequence to statistically vary the positions and concentrations of the impurity atoms. The variation causes variations in characteristics of the semiconductor devices fabricated. This is a serious problem in addition to the problem of requiring the semiconductor devices to be made minute. However, since no doping method capable of solving these problems has yet been known to the art, and there is an increasing demand for establishing a novel doping method
The present invention has been proposed in view of the above, and its object is to provide a doping method that can realize a shallow source-drain junction and low sheet resistance, improve the energy efficiency in fabricating semiconductor devices and be applied also to materials having restrictions on heat resistance without varying the characteristics of the semiconductor devices, and to provide a semiconductor device fabricated using the doping method.